1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for data processing in synchronization with a clock signal.
2. Description of the Related Art
With the realization of large-sized semiconductor integrated circuits, functional blocks (hard macros) already developed are reused as circuit patterns for labor savings of designing the semiconductor integrated circuits. Particularly, system vendors in the fields of consumer products, information, and communications provide a common interface specification standard for allowing the use of not only the hard macros self-designed but also the hard macros designed by other venders. The hard macros following the standard are called IP (Intellectual Property) or VC (Virtual Component) for registration. The IP or VC is utilized to allow the realization of combined hard macros supplied from various venders in the development of system LSIs. As examples of the hard macro, digital signal processors, A/D converters, and various memories are named.
Patent Document 1 (JP-A-2000-113025) describes the configuration and fabrication method of such the hard macro.
In the hard macro, its data input end is connected to a data input end of a flip flop (hereafter, it is called FF) on the input side and a data output end of an FF on the output side is connected to an output end of the hard macro through delay cells. Then, delay time of the delay cells is set so as to match data timing given to the FF on the input side from the data input end and data timing outputted to the data output end from the FF on the output side with timing of clock signals. Accordingly, the results of the hard macro are sequentially given to the subsequent hard macros in synchronization with the clock signals for assured processing.